The present invention relates generally to semiconductor processing and, more particularly, to a method for improving the process of forming low and high voltage threshold transistors on semiconductor wafers.
In the semiconductor device manufacturing industry, efforts are continuing for the purpose of further downsizing a single package semiconductor device. The initial efforts in the miniaturzation of a semiconductor device were directed to reduce the size of the semiconductor chip itself. By making the semiconductor chip smaller, the number of chips that could be obtained from one wafer was increased. In addition to bringing down manufacturing costs, the operating speed was increased since the movement distance of electrons between each element could be made shorter. Further, the development of microscopic processing technology decreased the chip size and allowed for the manufacture of a semiconductor device having the same functions. The current leading-edge design guideline for a device is less than 0.18 mu., and thus, it has become possible to place more than two million units on a single semiconductor chip.
As the size of the semiconductor device decreases, electric current from leakage gets more important. Leakage current limits the performance of the semiconductor device. Libraries with high voltage threshold (vt) transistors run at slower speeds but leak less power when they are inactive. Low vt cells, however, run faster but create more leakage current. Semiconductor device designers are constantly trying to find the right mix of low and high vt transistors in the device to optimize its performance. In addition, any reduction in processing steps usually means that the cost of making each device is cheaper and is highly desirable.
Therefore, what is needed, is a system and method that provides any savings of the cost in producing semiconductor devices. Further, optimization of the design of semiconductor devices is also needed.
The present invention provides a reduction in mask layers in producing low and high vt transistors. Moreover, the present invention also provides a method of optimizing the speed of the transistors.
The present invention provides a system and method for processing low voltage threshold transistors on a semiconductor wafer. The method may include: forming core transistors with drains on the semiconductor wafer; forming low voltage threshold transistors with drains on the semiconductor wafer; forming input output transistors with drains on the semiconductor wafer; forming a spacing layer over the core, low voltage and input output transistors; forming a first photoresist mask layer over the low voltage transistors; doping the drains of the core and the input output transistors, wherein the doping is a medium doping; forming a second photoresist mask layer over the input output transistors; and doping the drains of the core and the low voltage threshold transistors, wherein the doping is a medium doping.
A second method of the invention may include: forming core transistors with drains on the semiconductor wafer; forming low voltage threshold transistors with drains on the semiconductor wafer; forming input output transistors with drains on the semiconductor wafer; forming a first photoresist mask layer over the low voltage and the input output transistors; doping the drains of the core transistors, wherein the doping is a medium doping; forming a spacing layer over the core, low voltage and input output transistors; forming a second photoresist mask layer over the input output transistors; doping the drains of the core and the low voltage threshold transistors, wherein the doping is a medium doping; forming a third photoresist mask layer over the core and the low voltage transistors; and doping the drains of the input output transistors, wherein the doping is a medium doping.
Therefore, in accordance with the previous summary, objects, features and advantages of the present disclosure will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.